Renesas Electronics /R7FA2A1AB /DBG /DBGSTOPCR

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Interpret as DBGSTOPCR

DBGSTOP_IWDT=0, DBGSTOP_RPER=0, DBGSTOP_RECCR=0, DBGSTOP_WDT=0

Description

Debug Stop Control Register

Fields

DBGSTOP_IWDT	Mask bit for IWDT reset/interrupt 0 (0): Mask IWDT reset/interrupt 1 (1): Enable IWDT reset
DBGSTOP_WDT	Mask bit for WDT reset/interrupt 0 (0): Mask WDT reset/interrupt 1 (1): Enable WDT reset
Reserved	These bits are read as 00000000000000. The write value should be 00000000000000.
DBGSTOP_LVD	b18: Mask bit for LVD2 reset/interrupt (0:enable / 1:Mask)b17: Mask bit for LVD1 reset/interrupt (0:enable / 1:Mask)b16: Mask bit for LVD0 reset (0:enable / 1:Mask)
Reserved	These bits are read as 00000. The write value should be 00000.
DBGSTOP_RPER	Mask bit for RAM parity error reset/interrupt 0 (0): Enable RAM parity error reset/interrupt 1 (1): Mask RAM parity error reset/interrupt
DBGSTOP_RECCR	Mask bit for SRAM ECC error reset/interrupt 0 (0): Enable SRAM ECC error reset/interrupt 1 (1): Mask SRAM ECC error reset/interrupt.
Reserved	These bits are read as 000000. The write value should be 000000.

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